Electro-migration (EM) generally refers to transport of material caused by gradual movement of ions in a conductor due to momentum transfer between conducting electrons and diffusing metal atoms. Effects of EM may be important, for example, in applications where high direct current densities are used, such as in microelectronics and related structures. Physical and electrical properties of the structure may impact the EM. Additionally, as structure size decreases, practical significance of the EM effect increases. For this reason, it may be useful to both circuit and physical designers to check EM to predict circuitry viability.
EM checking typically involves calculating an average and root-mean-square (RMS) current through a metal segment. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations of a driver cell with a model of an interconnect may be used. These simulations, however, may be generally characterized as a “brute force” way of current determination. Stated differently, the aforementioned checking is based on a worst case approach, where only worse case scenarios are calculated. For example, a worst case scenario of current density is checked against EM guidelines.
Further, the aforementioned techniques may begin to break down as the number of interconnects start to increase. Typically, a complex IO may have more than one hundred thousand un-reduced parasitics, each of which needs to be checked against EM rules. Thus, it may become impractical to perform complete SPICE simulation for top level macros.
As the number of chip level interconnects touches the billion number mark, attempts to check were made using methods which resulted in run-time reductions. These methods, however, may have resulted in compromised accuracy.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.